: In microelectronic applications, the enhancement and scaling to the nanometer technology has
caused the SRAM memories to be used as one of the basic and essential components in wireless
communications in high performance server processors, multimedia applications and Systems
On-Chip (SoC). In the recent years, different SRAM cells have been designed and the 6T-SRAM structure is the most commonly used. However, the supply voltage variations and disconnection may eliminate the stored data. The Memristor is invented as one of the mostly used nano-devices, it can solve the problem due to the fast switching speed, high endurance and data retention, low power consumption, high integration density and CMOS compatibility. In this thesis, two novels high-performance non-volatile SRAM cell using the CMOS-Memristor technique for SRAM memory array are proposed. In the first design, SRAM has eight MOSFETs and two Memristors (8T2M-SRAM) and in the second design, SRAM has nine MOSFETs and two Memristors (9T2M-SRAM). The proposed SRAM cells are designed using 0.18µm CMOS TSMC Technology at 1.8v supply voltage. The design strategy is to reduce the power consumption, improve the Static Noise Margin (SNM) in the design of the non-volatile SRAM cell over the previous cell. The results show, write '0' and write '1' dynamic power consumption the 8T2MSRAM cell has a 10% improvement over the 6T-SRAM. Also, there is a 54% improvement in the dynamic power consumption the 9T2M-SRAM cell in the read '0' mode and a 71% improvement in the read '1' mode. It is worth noting that the simulations are performed in HSPICE.